This invention relates to clock generators, and more particularly to precision multi-phase clock generators using differential logic.
Many electronic devices and systems employ clock logic. High-speed clocks can be routed to flip-flops and registers to control sequencing of logical states and signals. Very precise clocks are required for some applications. In particular, multiple phases of a clock can be generated, allowing very precise selection of the clock""s phase.
For example, the period of a high-speed clock can be divided into 16 equally-spaced phases. FIG. 1 shows a prior-art clock generator that uses a ring oscillator to generate 16 clock phases. A ring of 16 inverters 12 passes a clock pulse around in a loop.
Each inverter 12 in the loop outputs a clock with a phase shift that depends on the position of the inverter within the loop. For example, the first inverter 12 outputs clock xcfx861 with a phase being ahead of clock xcfx865 by four inverter delays and ahead of clock xcfx869 by eight inverter delays. By controlling and matching the inverter delays, a clock period can be divided into 16 equally-spaced phases xcfx861 to xcfx8616.
While such ring oscillators are useful, various problems can occur. Erratic oscillation or multi-frequency oscillation can occur when 8 or more inverter stages are used in a loop. For example, when each of 8 inverter stages has one pole and a 90-degree phase shift, the total phase shift in the loop is 8xc3x9790 or 720 degrees. Then the loop can oscillate at either or both 720 degrees and 360 degrees. Such multiple oscillation can produce frequency overtones in the outputs. This is similar to a vibrating string on a musical instrument, which can vibrate at secondary frequencies or overtones.
Unfortunately, limiting the number of inverter stages in a loop also limits the number of phases that can be easily generated. It is desired to use few inverter stages to avoid overtone oscillation, but still provide enough taps to produce fine-resolution multi-phase clocks.